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ltc3706 1 3706fd typical application description secondary-side synchronous forward controller with polyphase capability the ltc ? 3706 is a polyphase capable secondary-side controller for synchronous forward converters. when used in conjunction with the ltc3705 gate driver and primary- side controller, the part creates a complete isolated power supply that combines the power of polyphase operation with the speed of secondary-side control. the ltc3706 has been designed to simplify the design of highly effcient, secondary-side forward converters. working in concert with the ltc3705, the ltc3706 forms a robust, self-starting converter that eliminates the need for the separate bias regulator that is commonly used in secondary-side control applications. in addition, a pro - prietary scheme is used to multiplex gate drive signals and dc bias power across the isolation barrier through a single, tiny pulse transformer. the ltc3706 provides remote sensing, accurate power good and overvoltage monitoring circuits to support preci - sion, high current applications. a linear regulator controller with thermal protection is also provided to simplify the generation of secondary-side bias voltage. the ltc3706 is available in a 24-lead ssop package. 36v-72v to 3.3v/20a isolated forward converter features applications n isolated 48v telecommunication systems n internet servers and routers n distributed power step-down converters n automotive and heavy equipment n secondary-side control for fast transient response n self-starting architecture eliminates need for separate bias regulator n proprietary gate drive encoding scheme reduces system complexity n polyphase ? operation reduces c in requirements n current mode control ensures current sharing n pll fixed frequency: 100khz to 500khz n 1% output voltage accuracy n true remote sense differential amplifer n power good output voltage monitor n high voltage linear regulator controller n wide supply range: 5v to 30v n available in a narrow 24-lead ssop package ndrv gnd pgnd vslmt uvlo boost ltc3705 bas21 fqt7n10 0.22f 10f 25v cmpsh1-4 1.2 l1 1.2h tg ts bg is t2 1f 162k l1: coilcraft ser2010-122 t1: pulse pa0807 t2: pulse pa0297 33nf 30m 1w 2m 2w si7336adp si7336adp 2 t1 ?? murs120 si7852dp si7852dp murs120 v cc 33nf 15k 1% 365k 1% 100k 2.2f 25v ss/flt fb/in + fs/in ? v in ? v in + 330f 6.3v 3 2.2f 16v 680pf czt3019 22.6k 1% 20k 102k 1% v out ? 3706 ta01 v out + ?? 1f 100v 3 fg sw sg v in ndrv v cc gnd pgnd phase slp mode regsd pt + i s + i s ? pt ? run/ss ltc3706 ith fb fs/sync l , lt, ltc, ltm, polyphase, burst mode, linear technology and the linear logo are registered trademarks and no r sense and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 6144194, other patents pending.
ltc3706 2 3706fd pin configuration absolute maximum ratings v cc ........................................................... C0.3v to 10v v in ........................................................... C0.3v to 33v sw ............................................................... C5v to 50v ndrv ......................................................... C0.3v to 13v ith, run/ss, v sout , v s + , v s C , regsd ....... C0.3v to 7v all other pins ............................................ C0.3v to 10v operating temperature range (note 2) ltc3706egn ....................................... C40c to 85c ltc3706ign ........................................ C40c to 85c junction temperature (note 3) ............................ 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................... 300c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 sg fg pgood mode phase fb ith run/ss v sout v s + v s ? gnd v cc pgnd pt + pt ? sw v in ndrv regsd i s + i s ? slp fs/sync t jmax = 125c, ja = 130c/w order information lead free finish tape and reel part marking package description temperature range ltc3706egn#pbf ltc3706egn#trpbf ltc3706egn 24-lead plastic ssop C40c to 85c ltc3706ign#pbf ltc3706ign#trpbf ltc3706ign 24-lead plastic ssop C40c to 85c lead based finish tape and reel part marking package description temperature range ltc3706egn ltc3706egn#tr ltc3706egn 24-lead plastic ssop C40c to 85c ltc3706ign ltc3706ign#tr ltc3706ign 24-lead plastic ssop C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
ltc3706 3 3706fd electrical characteristics the l indicates specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 7v, v in = 15v, gnd = pgnd = 0v, unless otherwise noted. symbol parameter conditions min typ max units main control loop v fb regulated feedback voltage (note 4) ith = 1.2v l 0.594 0.600 0.606 v i fb feedback input current (note 4) 2 100 na ?v fb(linreg) feedback voltage line regulation v in = 6v to 30v, ith = 1.2v 0.001 %/v ?v fb(loadreg) feedback voltage load regulation measured in servo loop, ith = 0.5v to 2v l C0.01 C0.1 % v ismax maximum current sense threshold r sense mode, 0v < v is C < 5v v is C = v cc , 0v < v is + < 2v (ct mode) 68 1.15 78 1.28 88 1.4 mv v v isoc over-current shutdown threshold r sense mode, 0v < v is C < 5v v is C = v cc , 0v < v is + < 2v (ct mode) 87 1.45 100 1.65 113 1.85 mv v g m transconductance amplifer g m 2.40 2.75 3.10 ms i run/ss(c) soft-start charge current v run/ss = 2v C4 C5 C6 a i run/ss(d) soft-start discharge current 3 a v run/ss run/ss pin on threshold v run/ss rising l 0.4 0.45 0.5 v t on,min minimum on-time 200 ns fg, sg r up fg, sg driver pull-up on resistance fg, sg low 1.5 2.7 fg, sg r down fg, sg driver pull-down on resistance fg, sg high 1.5 2.7 pt + , pt C r up pt + , pt C driver pull-up resistance pt + , pt C low 1.5 2.7 pt + , pt C r down pt + , pt C driver pull-down resistance pt + , pt C high 1.5 2.7 ?v fb(ov) output overvoltage threshold v fb rising 15 17 19 % v cc supply v ccop operating voltage range 5 10 v v ccreg regulated output voltage 6.6 7.0 7.4 v i cc supply current operating shutdown f osc = 200khz (note 5) v run/ss = gnd 4.2 240 ma a v uvlo uv lockout v cc rising l 4.52 4.60 4.70 v v hys uv hysteresis 0.4 v v in supply v inop operating voltage range 5 30 v i in supply current normal mode shutdown f osc = 200khz v run/ss = gnd 900 460 a a v inuvlo uv lockout v in rising l 3.90 4.30 4.51 v v inhys 0.2 v v regsd regsd shutdown threshold v regsd rising 4 v g m,regsd regsd transconductance 5 s
ltc3706 4 3706fd electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3706e is guaranteed to meet the performance specifca- tions over the 0c to 85c operating temperature range. specifcations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3706i is guaranteed and tested over the full C40c to 85c operating temperature range. note 3: junction temperature t j (in c) is calculated from the ambient tem- perature t a and the average power dissipation p d (in watts) by the formula: t j = t a + ja ? p d refer to the applications information section for details. note 4: the ltc3706 is tested in a feedback loop that servos v fb to a voltage near the internal 0.6v reference voltage to obtain the specifed ith voltage (v ith = 1.2v). note 5: operating supply current is measured in test mode. dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. see the typical performance characteristics section. symbol parameter conditions min typ max units oscillator and phase-locked loop i fs fs/sync pin sourcing current 20 a f low oscillator low frequency set point v fs/sync = gnd 165 200 235 khz f high oscillator high frequency set point v fs/sync = vcc 247 300 353 khz ?f (r fs ) oscillator resistor set accuracy 75k < r fs/sync < 175k C22 20 % f pll(max) maximum pll sync frequency 500 khz f pll(min) minimum pll sync frequency 75 khz pgood output v fbh /0.6 power good upper threshold v fb rising 115 117 119 % v fbl1 /0.6 power good lower threshold v fb rising 91.5 93 94.5 % v fbl2 /0.6 power good lower threshold v fb falling 89.5 91 92.5 % differential amplifer (v sense amp) ada gain v s C = gnd, 1v v s + 5v 0.990 1 1.010 v/v cmrr da common mode rejection ratio 75 db r in input resistance 80 k f bw C3db bandwidth 3 mhz the l indicates specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 7v, v in = 15v, gnd = pgnd = 0v, unless otherwise noted.
ltc3706 5 3706fd typical performance characteristics 100.0 101.5 101.0 100.5 99.5 3706 g07 99.0 v is /v is,max (%) temperature (c) ?50 50 75 100 25 ?25 0 125 440 470 460 450 430 3706 g08 420 v run/ss (mv) temperature (c) ?50 50 75 100 25 ?25 0 125 0 2 5 4 3 1 3706 g09 ?1 ?2 percent change in frequency (%) temperature (c) ?50 50 75 100 25 ?25 0 125 r = 175k f osc = 500khz r = 75k f osc = 100khz maximum current sense threshold vs temperature run/ss on threshold vs temperature oscillator frequency vs temperature t a = 25c, unless otherwise noted. input voltage (v) 5 5 6 7 98 3706 g01 4 6 7 10 3 supply current (ma) f osc = 200khz all gates: c load = 0 temperature (c) ?50 6.98 7.02 7.06 6.96 7.00 7.04 50 75 100 25 3706 g02 6.94 6.92 ?25 0 125 6.90 6.88 6.86 v cc output voltage (v) duty cycle (%) 0 60 80 100 60 3706 g03 40 20 20 40 80 0 r slp = 0 r slp = 50k 100k v is /v is,max (%) ith voltage (v) 0 60 80 100 2.0 2.5 1.5 3706 g04 40 20 0.5 1.0 3.0 0 v is /v is,max (%) is + , is ? common mode voltage (v) ?1 ?100 100 400 300 200 0 3 4 2 3706 g05 ?200 ?300 0 1 65 ?400 is pin source current (a) rs-mode: (i is + + i is ?) ct-mode: i is + 240 250 265 260 255 245 3706 g06 235 230 is pin source current (a) temperature (c) ?50 50 75 100 25 ?25 0 125 rs-mode: (i is + + i is ?) v is + = v is ? = 0v maximum current sense threshold vs ith voltage is pins source current is pins source current vs temperature v cc supply current vs input voltage v cc regulator output voltage vs temperature maximum current sense threshold vs duty cycle
ltc3706 6 3706fd 1.25 1.75 2.50 2.25 2.00 1.50 3706 g16 1.00 r ds,on () temperature (c) ?50 50 75 100 25 ?25 0 125 v cc = 7v load current (a) 0 85 90 95 2015 3706 g17 5 10 25 80 efficiency (%) v in = 36v v in = 72v 20s/div v in = 48v v out = 3.3v load step = 0a to 20a v out 100mv/div i out 10a/div 3706 g18 gate driver on-resistance vs temperature effciency (figure 5) load step (figure 5) typical performance characteristics t a = 25c, unless otherwise noted. v in supply voltage (v) 0 600.0 600.5 601.0 20 25 15 3706 g13 599.5 5 10 30 599.0 v fb (mv) 4.40 4.50 4.65 4.60 4.55 4.45 3706 g14 4.35 4.30 4.25 uvlo threshold voltage (v) temperature (c) ?50 50 75 100 25 ?25 0 125 v in rising v cc rising v cc voltage (v) 5 1.6 1.7 1.8 98 3706 g15 1.5 1.4 1.3 6 7 10 1.2 r ds,on () pull-down pull-up fb voltage line regulation undervoltage lockout vs temperature gate driver on-resistance vs v cc r fs (k) 50 400 500 600 150 175 125 3706 g10 300 200 100 75 100 200 0 frequency (khz) 3.995 4.010 4.005 4.000 3706 g11 3.990 v regsd (v) temperature (c) ?50 50 75 100 25 ?25 0 125 599.5 601.0 600.5 600.0 3706 g12 599.0 v fb (mv) temperature (c) ?50 50 75 100 25 ?25 0 125 oscillator frequency vs r fs regsd shutdown threshold vs temperature fb voltage vs temperature
ltc3706 7 3706fd pin functions sg (pin 1): gate drive for the synchronous mosfet. fg (pin 2): gate drive for the forward mosfet. pgood (pin 3): open-drain power good output. the fb pin is monitored to ensure that the output is in regulation. when the output is not in regulation, the pgood pin is pulled low. mode (pin 4): tie to either gnd or v cc to set the maxi- mum duty cycle at either 50% or 75% respectively. tie to ground through either a 200k or 100k resistor (50% or 75% maximum duty cycle) to disable pulse encoding. in this mode, normal pwm signals will be generated at the pt + pin, while a clock signal is generated at the pt C pin. phase (pin 5): control input to the phase selector. this pin determines the phasing of the controller clk relative to the synchronizing signal at the fs/sync pin. fb (pin 6): the inverting input of the main loop error amplifer. ith (pin 7): the output of the main loop error amplifer. place compensation components between the ith pin and gnd. run/ss (pin 8): combination run control and soft-start inputs. a capacitor to ground sets the ramp time of the output voltage. holding this pin below 0.4v causes the ic to shut down all internal circuitry. v sout , v s + , v s C (pins 9, 10, 11): v sout is the output of a precision, unity-gain differential amplifer. tie v s + and v s C to the output of the main dc/dc converter to achieve true remote differential sensing. this allows dcr error effects to be minimized. gnd (pin 12): signal ground. fs/sync (pin 13): combination frequency set and sync pin. tie to gnd or v cc to run at 200khz and 300khz respectively. place a single resistor to ground at this pin to set the frequency between 100khz and 500khz. to synchronize, drive this pin with a clock signal to achieve pll synchronization from 75khz to 500khz. sources 20a of current. slp (pin 14): slope compensation input. place a single resistor to ground to set the desired amount of slope compensation. i s C (pin 15): negative input to the current sense circuit. when using current sense transformers, this pin may be tied to v cc for single-ended sensing with a 1.28v maximum current trip level. i s + (pin 16): positive input to the current sense circuit. connect to the positive end of a current sense resistor or to the output of a current sense transformer. regsd (pin 17): this pin is used to prevent overheating of the external linear regulator pass device that generates the v cc supply voltage from the v in voltage. a current proportional to the voltage across the external pass device fows out of this pin. the ic shuts down the linear regulator when the voltage on this pin exceeds 4v. place a resistor (or a resistor and capacitor in parallel) between this pin and gnd to limit the temperature rise of the external pass device. ndrv (pin 18): drive output for the external pass device of the v cc linear regulator. connect to the base (npn) or gate (nmos) of an external n-type device. v in (pin 19): connect to a higher voltage bias supply, typically the output of a peak detected bias winding. when not used, tie together with the v cc and ndrv pins. sw (pin 20): connect to the drain of the synchronous mosfet. this input is used for adaptive shoot-through prevention and leading edge blanking. pt C , pt + (pins 21, 22): pulse transformer driver outputs. for most applications, these connect to a pulse trans - former (with a series dc blocking capacitor). the pwm information is multiplexed together with dc power and sent through a single pulse transformer to the primary side. this information may be decoded by the ltc3705 gate driver and primary-side controller. pgnd (pin 23): gate driver ground pin. v cc (pin 24): main v cc input for all driver and control circuitry.
ltc3706 8 3706fd block diagram 4v sb ? + ? + 16 15 i s + i s ? 7 i th 6 fb 14 slp 5 phase 4 mode 8 9 run/ss v sout 11 v s ? v s + 40k 40k 13 fs/sync 2v 2 32 c ? + ? + ? + ? + ? + ea 2.5v run/ss 0.60v ? + c ? + c 0.25v 3.2v i trp skip blank wait ovp r q s dmax pwm reset dominant ovp v cc v cc pgnd v cc fg pgnd wait zero crossing detect drive type r q s ot latch drive/dmax control osc and pll soft- start 4v sb fb v ccuv shdn sslow wait ot oc oc uvlo v inuv restrt1 slope comp 1 pgood/ovp driver encoding and logic blank dmax 23 sg 0.2v 1 sw 20 pt + 2 ? + v cc 22 pt ? pulse xfmr 21 v in 19 v cc v in g m = 5s 24 regsd 17 pgood 3 gnd 12 ndrv 18 reg 4v sb 4v sb 1.24v shdn 60k 5v dc to 30v dc 5v dc to 10v dc a 4v sb 4v ovp 3706 bd fb 0.6v v cc uvlo v ref 275k v in 40k v cc shdn (4.25/4.5) v ccuv v sense amp 40k 10 a ? ? g m = 2.8ms ? + c overcurrent
ltc3706 9 3706fd operation main control loop the ltc3706 is designed to work in a constant frequency, current mode 2-transistor forward converter. during normal operation, the primary-side mosfets (both top and bottom) are clocked on together with the forward mosfet on the secondary side. this applies the refected input voltage across the inductor on the secondary side. when the current in the inductor has ramped up to the peak value as commanded by the voltage on the ith pin, the current sense comparator is tripped, turning off the primary-side and forward mosfets. to avoid turning on the synchronous mosfet prematurely and causing shoot-through, the voltage on the sw pin is monitored. this voltage will usually fall below 0v soon after the primary-side mosfets have turned completely off. when this condition is detected, the synchronous mosfet is quickly turned on, causing the inductor current to ramp back downwards. the error amplifer senses the output voltage, and adjusts the ith voltage to obtain the peak current needed to maintain the desired main-loop output voltage. the ltc3706 always operates in a continuous current, synchronous switching mode. this ensures a rapid transient response as well as a stable bias supply voltage at light loads. a maximum duty cycle (either 50% or 75%) is internally set via clock dividers to prevent saturation of the main transformer. in the event of an overvoltage on the output, the synchronous mosfet is quickly turned on to help protect critical loads from damage. gate drive encoding since the ltc3706 controller resides on the secondary side of an isolation barrier, communication to the primary-side power mosfets is generally done through a transformer. moreover, it is often necessary to generate a low voltage bias supply for the primary-side gate drive circuitry. in order to reduce the number of isolated windings present in the system, the ltc3706 uses a proprietary scheme to encode the pwm gate drive information and multiplex it together with bias power for the primary-side drive and control, using a single pulse transformer. note that, unlike optoisolators and other modulation techniques, this multiplexing scheme does not introduce a signifcant time delay into the system. for most forward converter applications, the pt + and pt C outputs will contain a pulse-encoded pwm signal. these outputs are driven in a complementary fashion with an essentially constant 50% duty cycle. this results in a stable volt-second balance as well as an effcient transfer of bias power across the pulse transformer. as shown in figure 1, the beginning of the positive half-cycle coincides with the turn-on of the primary-side mosfets. likewise, the beginning of the negative half-cycle coincides with the maximum duty cycle (forced turn-off of primary switches). at the appropriate time during the positive half-cycle, the end of the on-time (pwm going low) is signaled by briefy applying a zero volt differential across the pulse transformer. figure 1 illustrates the operation of this multiplexing scheme. the ltc3705 primary-side controller and gate driver will decode this pwm information as well as extract the power needed for primary-side gate drive. figure 1. gate drive encoding scheme (v mode = gnd) ?7v 7v ?7v 7v 150ns 1 clk per duty cycle = 15% v pt1 + ? v pt1 ? 150ns 3706 f01 1 clk per duty cycle = 0%
ltc3706 10 3706fd operation values using the slp pin as shown in table 1. note that the amount of slope compensation doubles when the duty cycle exceeds 50%. table 1 slp pin slope (d < 0.5) slope (d > 0.5) gnd 0.05 ? i smax ? f osc 0.1 ? i smax ? f osc v cc none none 400k to gnd 0.1 ? i smax ? f osc 0.2 ? i smax ? f osc 200k to gnd 0.15 ? i smax ? f osc 0.3 ? i smax ? f osc 100k to gnd 0.25 ? i smax ? f osc 0.5 ? i smax ? f osc 50k to gnd 0.5 ? i smax ? f osc 1.0 ? i smax ? f osc in table 1 above, i smax is the maximum current limit, and f osc is the switching frequency. current sensing and current limit for current sensing, the ltc3706 supports either a current sense resistor or a current sense transformer. the current sense resistor may either be placed in series with the inductor (either high side or ground lead sensing), or in the source of the forward switch. if a current sense transformer is used, the i s C input should be tied to v cc and the i s + pin to the output of the current sense transformer. this causes the gain of the internal current sense amplifer to be reduced by a factor of 16, so that the maximum current sense voltage (current limit) is increased from 78mv to 1.28v. an internal, adaptive leading edge blanking circuit ensures clean operation for switch current sensing applications. current limit is achieved in the ltc3706 by limiting the maximum voltage excursion of the error signal (ith volt - age). note that if slope compensation is used, the precise value at which current limit occurs will be a function of duty cycle (see the typical performance characteristics section). if a short circuit is applied, an independent overcurrent comparator may be tripped. in this case, the ltc3706 will enter a hiccup mode using the soft-start circuitry. self-starting architecture when the ltc3706 is used in conjunction with the ltc3705 primary-side controller and gate driver, a complete self - starting isolated supply is formed. when input voltage is frst applied in such an application, the ltc3705 will begin switching in an open-loop fashion, causing the main output to slowly ramp upwards. this is the primary-side soft-start mode. on the secondary side, the ltc3706 derives its operating bias voltage from a peak-charged capacitor. this peak-charged voltage will rise more rapidly than the main output of the converter, so that the ltc3706 will become operational well before the output voltage has reached its fnal value. when the ltc3706 has adequate operating voltage, it will begin the procedure of assuming control from the primary side. to do this, it frst measures the voltage on the power supplys main output and then automatically advances its own soft-start voltage to correspond to the main output voltage. this ensures that the output voltage increases monotonically as the soft-start control is transferred from primary to secondary. the ltc3706 then begins sending pwm signals to the ltc3705 on the primary side through a pulse transformer. when the ltc3705 has detected a stable signal from the secondary controller, it transfers control of the primary switches over to the ltc3706, beginning the secondary-side soft-start mode. the ltc3706 continues in this mode until the output voltage has ramped up to its fnal value. if for any reason, the ltc3706 either stops sending (or initially fails to send) pwm information to the ltc3705, the ltc3705 will detect a fault and initiate a soft-start retry. (see the ltc3705 data sheet.) slope compensation slope compensation is added at the input of the pwm comparator to improve stability and noise margin of the peak current control loop. the amount of slope compen - sation can be selected from one of fve preprogrammed
ltc3706 11 3706fd operation frequency setting and synchronization the ltc3706 uses a single pin to set the operating frequency, or to synchronize the internal oscillator to a reference clock with an on-chip phase-locked loop (pll). the fs pin may be tied to gnd, v cc or have a single resistor to gnd to set the switching frequency. if a clock signal (>2v) is detected at the fs pin, the ltc3706 will automatically synchronize to the rising edge of the reference clock. table 2 summarizes the operation of the fs pin. for synchronization between multiple ltc3706s, the pt + pin of one ltc3706 can be used as a master clock reference and tied to the fs pin of the other ltc3706s. table 2 fs pin switching frequency gnd 200khz v cc 300khz r fs to gnd f osc (hz) = 4r fs C 200k reference clock f osc = f ref (75khz to 500khz) this will cause all ltc3706s to operate at the same fre - quency. the phase angle of each ltc3706 that is being synchronized can be set by using the phase pin. this pin can be tied to gnd, v cc or have a single resistor to v cc to set the phase angle (delay) of the internal oscillator relative to the incoming sync signal on the fs pin. any one of fve preset values can be selected as summarized in table 3. table 3 phase pin ltc3706 phase delay gnd 0 v cc 180 226k to v cc 60 113k to v cc 90 56.2k to v cc 120 soft-start the soft-start circuitry has fve functions: 1) to provide a shutdown, 2) to provide a smooth ramp on the output voltage during start-up, 3) to limit the output current in a short-circuit situation by entering a hiccup mode, 4) to limit the maximum power dissipation in the external linear regulator via the regsd pin, and 5) to communicate fault and shutdown information between multiple ltc3706s in a polyphase application. when the run/ss pin is pulled to gnd, the chip is placed into shutdown mode. if this pin is released, the run/ss pin is initially charged with a 50a current source. after the run/ss pin gets above 0.5v, the chip is enabled. at the instant that the ltc3706 is frst enabled, the run/ss voltage is rapidly preset to a voltage that will correspond to the main output voltage of the dc/dc converter. (see the self-starting architecture section.) after this preset interval has completed, the normal soft-start interval begins and the charging current is reduced to 5a. the external soft-start voltage is used to internally ramp up the 0.6v reference (positive) input to the error amplifer. when fully charged, the run/ss voltage remains at 3v. in the event that the sensed switch or inductor current exceeds the overcurrent trip threshold, an internal fault latch is tripped. this latch is also tripped when the regsd voltage exceeds 4v (see the linear regulator section). when such a fault is detected, the ltc3706 immediately goes to zero duty cycle and initiates a soft-start retry. prior to discharging the soft-start capacitor, however, the ltc3706 frst puts a voltage pulse on the run/ss pin, which trips the fault latch in any other ltc3706 that shares the run/ss. this ensures an orderly shutdown of all phases in a polyphase application. after the soft-start capacitor is fully discharged, the ltc3706 attempts a restart. if the fault is persistent, the system enters a hiccup mode.
ltc3706 12 3706fd operation note that in self-starting secondary-side control applica - tions (with the ltc3705), the presence of the lt3706 bias voltage is dependent upon the regular switching of the primary-side mosfets. therefore, depending on the details of the application circuit, the ltc3706 may lose its bias voltage after a fault has been detected and before completing a soft-start retry. in this case, the hiccup- mode operation is actually governed by the ltc3705 soft-start circuitry. (see the ltc3705 data sheet.) drive mode and maximum duty cycle although the ltc3706 is primarily intended to be used with the ltc3705 in 2-transistor forward applications, the mode pin provides the fexibility to use the ltc3706 in a wide variety of additional applications. this pin can be used to defeat the gate drive encoding scheme, as well as change the maximum duty cycle from its default value of 50%. the use of the mode pin is summarized in table 4. when the gate drive encoding scheme is defeated, a standard pwm-style signal will be present at the pt + pin and a reference clock (in phase with the pwm signal) will be present at the pt C pin. these outputs can be used in standalone applications (without the ltc3705) to drive the gates of mosfets in a conventional manner. table 4 mode pin pt + /pt C mode (max duty cycle) intended application gnd encoded pwm (d max = 50%) 2-switch forward with ltc3705 v cc encoded pwm (d max = 75%) 1-switch forward 200k to gnd standard pwm (d max = 50%) 2-switch forward standalone 100k to gnd standard pwm (d max = 75%) 1-switch forward standalone power good/overvoltage protection this circuit monitors the voltage on the fb input. the open-drain pgood output will be logic high if the voltage on the fb pin is within +17%/C7% of 0.6v. if the voltage on the fb pin exceeds 117% of 0.6v (0.7v), an overvoltage (ovp) is detected. for overvoltage protection, the sec - ondary-side synchronous mosfet is turned on while all other mosfets are turned off. this protection mode is not latched, so that the overvoltage detection is cleared if the fb voltage falls below 115% of 0.6v (0.69v). linear regulator operation the ltc3706 provides a linear regulator controller that drives an external n-type pass device. this controller is used to create a 7v dc bias from the peak-charged secondary bias voltage (8v to 30v). internal divider resistors are used to establish a regulation voltage of 7v at the v cc pin. an auxiliary bias supply with a regulated voltage greater than 7v may be applied to the v cc pin to bypass (bootstrap) the linear regulator. this improves effciency and also helps to avoid overheating the linear regulator pass device. thermal protection for the linear regulator pass device is also provided by means of the regsd pin. a current is sourced from this pin that is proportional to the voltage across the linear regulator pass device (v in C v cc ). since the v cc load current is essentially constant for a given switching frequency and choice of power mosfets, the power dissipated in the external pass device will only vary with the voltage across it. thus, a single resistor may be placed between the regsd pin and gnd to develop a volt - age that is proportional to the power in the external pass device. an additional parallel capacitor can also be used to account for the thermal time constant associated with the external pass device itself. when the voltage on the regsd pin exceeds 4v, an overtemperature fault occurs and the ltc3706 attempts a soft-start retry.
ltc3706 13 3706fd applications information start-up considerations in self-starting applications, the ltc3705 will initially begin the soft-start of the converter in an open-loop fashion. after bias is obtained on the secondary side, the ltc3706 assumes control and completes the soft-start interval. in order to ensure that control is properly transferred from the ltc3705 (primary-side) to the ltc3706 (secondary-side), it is necessary to limit the rate of rise on the primary-side soft-start ramp so that the ltc3706 has adequate time to wake up and assume control before the output voltage gets too high. this condition is satisfed for many applications if the following relationship is maintained: c ss,sec c ss pri however, care should be taken to ensure that soft-start transfer from primary-side to secondary-side is completed well before the output voltage reaches its target value. a good design goal is to have the transfer completed when the output voltage is less than one-half of its target value. note that the fastest output voltage rise time during pri - mary-side soft-start mode occurs with maximum input voltage and minimum load current. the open-loop start-up frequency on the ltc3705 is set by placing a resistor from the fb/in + pin to gnd. although the exact start-up frequency on the primary side is not critical, it is generally good practice to set this approxi- mately equal to the operating frequency on the secondary side. the fs/in C start-up resistor for the ltc3705 may be selected using the following: f pri (hz) = 3.2 ? 10 10 r fs/in ? + 10k in the event that the secondary-side circuitry fails to properly start up and assume control of switching, there are several fail-safe mechanisms to help avoid overvoltage conditions. first, the ltc3705 contains a volt-second clamp that will keep the primary-side duty cycle at a level that cannot produce an overvoltage condition. second, the ltc3705 contains a time-out feature that will detect a fault if the ltc3706 fails to start up and deliver pwm signals to the primary side. finally, the ltc3706 has an independent overvoltage detection circuit that will crowbar the output of the dc/dc converter using the synchronous mosfet switch. in the event that a short circuit is applied to the output of the dc/dc converter prior to start-up, the ltc3706 will generally not receive enough bias voltage to operate. in this case, the ltc3705 will detect a fault for one of two reasons: 1) the start-up time-out feature will be activated since the ltc3706 never sends signals to the primary side or 2) the primary-side overcurrent circuit will be tripped because of current buildup in the output inductor. in either case, the ltc3705 will initiate a shutdown followed by a soft-start retry. see the ltc3705 data sheet for further details. operation slave mode operation when two or more ltc3706 devices are used in polyphase systems, one device becomes the master controller, while the others are used as slaves. slave mode is activated by connecting the fb pin to v cc . in this mode, the ith pin becomes a high impedance input, allowing it to be driven by the master controller. in this way, equal inductor currents are established in each of the individual phases. also, in slave mode the soft-start charge/discharge currents are disabled, allowing the master device to control the charging and discharging of the soft-start capacitor.
ltc3706 14 3706fd applications information bias supply generation figure 2 shows a commonly used method of developing a v cc bias supply for the ltc3706. during start-up, bias winding 1 uses a peak detection method to rapidly develop a v in voltage for the ltc3706, which in turn drives the linear regulator that generates the v cc voltage (7v). when the main output of the converter is in regulation, winding 2 (confgured as a forward-style output) is designed to produce a regulated auxiliary voltage of approximately 7.5v to 8.5v. since the auxiliary voltage is greater than that of the linear regulator, the linear regulator will effectively be shut down. note that the output inductor l1 must be adequately large so that its ripple current is continuous given the amount of v cc load current, thereby providing a stable output voltage. figure 2. typical bias supply confguration v in ltc3706 4.7 mbro530 bas21 fmmt491a 1mh ndrv regsd r regsd c regsd 4.7f 16v winding 1 nb1 3706 f02 main transformer winding 2 nb2 ? ? bas21 1 1f 50v v cc ? the turns ratio (nb1) of the bias winding 1 should be cho - sen to ensure that there is adequate voltage to operate the ltc3706 over the entire range for the dc/dc converters input bus voltage (v bus ). this may be calculated using: nb1 = v cc(min) + 1.5v v bus(min) v cc(min) can be as low as 5v (if this provides adequate gate drive voltage to maintain acceptable effciency) or as high as 7v. for v cc(min) = 6v and v bus = 36v to 72v, this would mean a turns ratio of nb1 0.21 and a v in voltage range at the ltc3706 of 7.5v to 15v. using the bias circuit of figure 2, the linear regulator would normally operate only for a brief interval during the initial soft-start ramp of the main output voltage. under some fault conditions (e.g., output overload), the auxiliary voltage produced by bias winding 2 may decrease below 7v, causing the linear regulator to again supply the v cc bias current. since the amount of power dissipation in the linear regulator pass device may be quite high, it can take considerable board area when the linear regulator pass device is sized to handle this power continuously. as an alternative, the regsd pin may be used to effectively detect an overtemperature condition on the linear regulator pass device and generate a shut down (soft-start retry) before overheating occurs. this allows for the use of a small (e.g., sot-23) package for the linear regulator pass device.
ltc3706 15 3706fd applications information the regsd resistor should be selected based upon the steady-state (dc) thermal impedance of the linear regula- tor pass device. r regsd = 960k ja ? i cc(max) t rise(max) where ja is the dc thermal impedance of the linear regulator pass device and t rise(max) is the maximum junction temperature rise desired for the pass device. the value for i cc(max) depends heavily on the particular switching mosfets used, as well as on the details of overall system design. note that it may include the bias current associated with the primary-side gate driver and controller, if the ltc3705 is being used. the value for i cc is best determined experimentally and then guard banded appropriately to establish i cc(max) . using the typical ap - plication circuit on the frst page of this data sheet as an example, if a sot-23 mosfet is chosen, we might have ja = 150c/w, t rise(max) = 50c and i cc(max) = 35ma so that r regsd 100k. in this case, the linear regulator can run continuously for any v in voltage that is less than: 4v = (v in C v cc )(5s)(r regsd ) v in(max) = 640k r regsd ? ? ? ? ? ? + 7v or 13.4v. in addition, a capacitor may be added in parallel with the regsd resistor to delay the thermal shutdown and thereby account for the thermal time constant of the pass device. when using a delay capacitor, care must be taken to ensure that the safe operating area (soa) of the pass device is not exceeded. the capacitor should be chosen to provide a time constant that is somewhat faster than the thermal time constant of the pass device in the system. this technique will allow for much higher transient power dissipation, which is particularly useful in larger (polyphase) systems that have a higher v cc bias current. for the above sot-23 example, a capacitor c regsd = 1f provides a linear regulator shutdown delay given by: t shdn = c regsd ( ) r regsd ( ) ln 1 1? 640k v in ? 7 ( ) r regsd ? ? ? ? ? ? ? ? ? ? ? ? or 33ms at v in = 30v. this delay provides ample time for linear regulator operation during soft-start, while providing protection for the pass device during fault conditions such as input overvoltage or output overcurrent. current sensing the ltc3706 provides considerable fexibility in current sensing techniques. it supports two main methods: 1) resistive current sensing and 2) current transformer cur - rent sensing. resistive current sensing is generally simpler, smaller and less expensive, while current transformer sens - ing is more effcient and generally appropriate for higher (>20a) output currents. for resistive current sensing, the sense resistor may be placed in any one of three different locations: high side inductor, low side inductor or low side switch, as shown in figure 3. sensing the inductor
ltc3706 16 3706fd applications information ltc3706 78mv max i s + i s ? 3706 f03a ? ? ltc3706 78mv max i s + i s ? 3706 f03c ? ? figure 3a. high side inductor: easier layout, low noise, accurate figure 3c. switch current sensing: easy layout, accurate, higher effciency, high v out capable figure 3. current sensing techniques ltc3706 78mv max i s + i s ? 3706 f03b ? ? ltc3706 v cc 1.28v max trip 5w to 50 i s + i s ? 3706 f03d ? ? ? ? figure 3b. low side inductor: accurate, low noise, high v out capable figure 3d. current transformer: highest effciency, high v out capable current (high side or low side) is generally less noisy but dissipates more power than sensing the switch current (figures 3a and 3b). high side inductor current sensing provides a more convenient layout than low side (no split ground plane), but can only be used for output voltages up to 5.5v, due to the common mode limitations of the current sense inputs (i s + and i s C ). for most applications, low side switch current sensing will be a good solution (figure 3c). for high current applications where effciency (power dis - sipation) is very important, a current sense transformer may be used. as shown in figure 3d, the i s C pin should be tied off to v cc when a current sense transformer is used. this causes the i s + pin to become a single ended (nondifferential) current sense input with a maximum current sense voltage of 1.28v. figure 3d shows a typical application circuit using a current transformer.
ltc3706 17 3706fd figure 4. connections for polyphase operation ndrv uvlo ltc3705 (master) v cc ss/flt fb/in + fs/in ? v in ? v in + v in ndrv v cc pt + pt ? run/ss ltc3706 (master) ith 3706 f04 v out + v bias fb fs/sync ?? ndrv ss/flt ltc3705 (slave) v cc uvlo fb/in + fs/in ? v in ndrv v cc pt + pt ? run/ss ltc3706 (slave) ith fb phase fs/sync ?? applications information polyphase applications figure 4 shows the basic connections for using the ltc3705 and ltc3706 in polyphase applications. one of the phases is always identifed as the master, while all other phases are slaves. for the ltc3705 (primary side), the master monitors the v in voltage for undervoltage, performs the open-loop start-up and supplies the initial v cc voltage for the master and all slaves. the ltc3705 slaves simply stand by and wait for pwm signals from their respective pulse transformers. since the ss/flt pins of master and slave ltc3705s are interconnected, a fault (overcurrent, etc.) on any one of the phases will perform a shutdown/restart on all phases together. the ltc3705 is put into slave mode by omitting the resistor on fs/in C . for the ltc3706, the master performs soft-start and voltage-loop regulation by driving all slaves to the same current as the master using the ith pins. faults and shutdowns are communicated via the interconnection of the run/ss pins. the ltc3706 is put into slave mode by tying the fb pin to v cc .
ltc3706 18 3706fd typical applications ndrv gnd pgnd vslmt uvlo boost ltc3705 bas21 fqt7n10 0.22f 2.2nf 250v 1nf 100v 1nf 100v 10f 25v cmpsh1-4 1.2 l2 1.2h 10 0.25w 10 0.25w tg ts bg is t2 1f 162k l1: vishay ihlp-2525cz-01 l2: coilcraft ser2010-122 t1: pulse pa0807 t2: pulse pa0297 33nf 30 1w 2m 2w si7336adp si7336adp 2 t1 1:2 9:2 ?? murs120 murs120 v cc 33nf 1nf 15k 1% 365k 1% 100k 2.2f 25v ss/flt fb/in + fs/in ? v in ? v in + l1 1h 330mf 6.3v 3 1f 2.2f 16v 470pf 680pf fg sw sg v in ndrv czt3019 v cc gnd pgnd phase slp mode regsd pt + i s + i s ? pt ? run/ss ltc3706 ith 22.6k 1% 100k 20k 680pf 102k 1% v out ? 3706 f05 v out + fb fs/sync 0.1f 5k 1nf ?? 1f 100v 1f 100v 3 100 100 100 100 si7852dp si7852dp figure 5. 36v-72v to 3.3v/20a isolated forward converter (see typical performance characteristics)
ltc3706 19 3706fd typical applications 36v to 72v to 12v/20a isolated forward converter. can be paralleled for higher output power 3 6 8 1 t2 4 5 12 150 v aux 150pf 10nf 4.7nf ?v out ?v out ?v out +v out 470pf 470pf 10nf 1nf 1f 100 100k v aux 100k l1: coilcraft do1606t-104mlc l5: vishay ihlp2525czerr68m01 l6: pulse pa1494.242 t1: pulse pa0955 (6:6:3) t2: pulse pa1954nl (1:1:1) t3: ice ct02-100 (1:100) t4: coilcraft da2318-alc (1:1.5) npns: diodes fmmt619 pnps: diodes fmmt718 2.2nf 250v murata ga343qr7gd222kw01l 68f 16v sanyo 16tqc68m 110k 15.0k 365k 100k ?v in +v in 0.1f 2.2nf 250v 10m 1.5w 5.1 1/2w 1nf 100v b 11 8 ? ? ? t1 5 3 4 2 100 330 7.5 t3 bas21 3 ?v out i s + 4 2 1 100pf 680pf 200v si7450dp 3 10nf 10pf 1f 5.1k 150 100 mmbt2907a fcx491a a fb/in + is gnd gate pgnd ndrv vslmt fs/in ? v cc fdc2512 ssflt uvlo ltc3725 2.2f hat2244wp 2 hat2244wp 2 sw 10f 510 68f 16v 2 2.2f 100v 3 2.2f 100v 1nf 100v l6 2.4h 5.1 1/2w 10f 25v 6.2k 604 3706 ta03 11.5k pt + pt ? fb bat21 bas21 sw 36v mmbz5258b 4 a b t4 cmpsh1-4 cmpsh1-4 ? ? 6 1 0.1f 3 ?v out 100k 0.1f si2303bds l1 100h 2n7002 390 gnd pgnd regsd phase run/ss ith slp fs/sync fg sw i s ? v cc mode ndrv v in i s + sg i s + ltc3706 cmpsh1-4 cmpsh1-4 68k 68pf + ? l5 0.68h ? ?
ltc3706 20 3706fd package description gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) .337 ? .344* (8.560 ? 8.738) gn24 (ssop) 0204 1 2 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 161718192021222324 15 14 13 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc3706 21 3706fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number d 7/11 updated electrical characteristics updated table 3 added new typical application schematics updated related parts 3, 4 11 19, 22 22 (revision history begins at rev d)
ltc3706 22 3706fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2005 lt 0711 rev d ? printed in usa related parts typical application 36v to 72v to 5v/20a isolated forward converter t2 1:2 3, 41 8 1f 0.1f 124k 100 100 100 0.002 1w 100k 100k 15.0k 365k 2n7002 5, 6 1n4148w 536 1k 1/4w va va si7336adp si7336adp si7450dp l2 0.87h cmpsh1-4 mmbz5236b 7.5v 5.1k 10pf v sw ?? gnd pgnd phase fg is gate ndrv is gate ndrv sw sg v cc ndrv v in mode regsd fs/sync 100k slp 6.2k 604 1.2 1/4w 2.2nf 3706 ta02 47pf 2.2f ?v out +v out 100f 6.3v 3 4.7f 25v 1.0f 100v +v in ?v in 1.0f 100v 3 1nf 200v 220f 6.3v 4.42k 510 0.022 1w 7 9 5 t1 3 4 2 ? ? ? 2.4 14w v sw 33nf 33nf 220f 6.3v sanyo 6tpe220mi 2.2nf 250v murata ga343qr7gd222kw01l l1: vishay ihlp-2525czer1r0m-01 l2: cooper hc1-r87 t1: pulse pa0811 (4:4:2) t2: pulse pa0297 2(1.5mh):1:1 470nf 1f fdc2512 (sot6) 470pf fb/in + fs/in ? ssflt uvlo ltc3725 v cc ith pt + ltc3706 fcx491 fb pt ? run/ss is + is ? + 330pf 330pf 3.01k 100 l1 1h 2.2nf 250v 1.5nf 50v part number description comments ltc3726/ltc3725 isolated synchronous no opto-forward controller chip set ideal for medium power 24v or 48v input applications lt1952/lt1952-1 isolated synchronous forward controllers ideal for medium power 24v or 48v input applications ltc3723-1/ltc3723-2 synchronous push-pull and full-bridge controllers high effciency with on-chip mosfet drivers ltc3721-1/ltc3721-2 nonsynchronous push-pull and full-bridge controllers minimizes external components, on-chip mosfet drivers ltc3722/ltc2722-2 synchronous isolated full-bridge controllers ideal for high power 24v or 48v input applications lt3748 100v no opto-flyback controller 5v v in 100v, boundary mode operation, msop-16 with extra high voltage pin spacing lt3758 boost, flyback, sepic and inverting controller 5.5v v in 100v, 100khz to 1mhz fixed frequency, 3mm w 3mm dfn-10 and msop-10e package ltc1871/ltc1871-1 ltc1871-7 wide input range, no r sense ? low quiescent current flyback, boost and sepic controller 2.5v v in 36v, burst mode ? operation at light load, msop-10 ltc3803/ltc3803-3 ltc3803-5 flyback dc/dc controller with fixed 200khz or 300khz operating frequency v in and v out limited only by external components, 6-pin thinsot? package lt3575 isolated flyback no opto-converter with 2.5a/60v power switch 3v v in 40v, boundary mode, up to 14w, tssop-16 package

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